1. Field of the Invention
The present invention relates to power electronics and, more specifically, to a switching voltage regulator.
2. Description of the Related Arts
Switching voltage regulators are commonly utilized in a wide variety of electronic circuits because of their high power conversion efficiency. A common concern in the design and use of switching regulators is switching loss. Generally, switching loss increases as the switching frequency of the regulator increases. Thus, to reduce switching loss, a slower switching frequency should be used. However, as the switching frequency decreases, the load transient response of the switching regulator also becomes slower. A slow transient response may cause the output voltage to deviate from its desired value because the regulator cannot respond quickly enough to changing load demands.
FIG. 1A is a block diagram illustrating a conventional switching regulator 100. Switching regulator 100 comprises boost converter 102 and PWM controller 104. Other conventional circuit components are omitted for clarity of description. Boost converter 102 receives input voltage VIN and supplies regulated output voltage VOUT to drive a load 106. PWM controller 104 controls switching of boost converter 102 via control signal PWM_CTRL according to a conventional pulse width modulation (PWM) technique. PWM_CTRL comprises a series of variable width pulses outputted at a fixed frequency. PWM controller 104 outputs one pulse of PWM_CTRL for each clock cycle of CLK_IN. PWM controller 104 also monitors various characteristics of boost converter 102 via feedback control signal FB_CTRL, and varies the duty cycle of PWM_CTRL to achieve the desired output power regulation.
FIG. 1B is a waveform diagram illustrating the transient response problem in the context of conventional switching regulator 100. The waveforms illustrate a load current IL through load 106, clock signal CLK_IN, and PWM control signal PWM_CTRL. Between times t0 and t1, load current IL remains constant and PWM_CTRL controls switching of boost controller 102 according to a fixed duty cycle. At a time t1, the load demand changes and load current IL increases. To meet the increased load demand, PWM controller 104 must increase the duty cycle of PWM_CTRL. However, PWM controller 104 cannot begin adjusting the duty cycle of PWM_CTRL until the start of the next clock cycle at time t2. Thus, there is a transient delay, td=t2−t1, during which VOUT may begin to droop. This transient delay problem is exacerbated further as switching frequency is reduced. As a result, designers and users of conventional switching regulators are faced with an undesirable tradeoff between power efficiency and transient response when selecting a switching frequency.